Integrated circuit memory devices are made which can operate with different power supply voltages. For example, a typical memory chip can operate with a power supply voltage of 5 V.+-.10% or with a power supply voltage of 3.3 V.+-.0.3 V. For an integrated circuit memory device which includes non-volatile single floating gate transistor memory cells which are to be programmed or erased, or read, it is necessary for certain read operations to provide a voltage of approximately 5 V to the gates of the cells. A voltage of about 5 V is sufficient to deliver enough cell current for reliable sensing in cells having an erase threshold voltage of about 3 V which is the highest practical maximum in existing floating gate transistor cells in non-volatile memories. Where the power supply voltage is 5 V, the necessary voltage required for reading can be derived directly from the power supply itself. However, where the power supply voltage is nominally 3.3 V, it is necessary to boost this voltage up to a value in excess of 4 V and preferably about 5 V for the required read operations. This can be done by a voltage boost circuit or a pump circuit. Voltage boost circuits are known and are not discussed in detail herein. They include a boot capacitor across which the output boosted voltage is provided. The boosted level is determined by the ratio of the boot capacitor to the amount of capacitance which is connected on the supply line on which the voltage is to be boosted. If this capacitance can be reduced, then the size of the boot capacitor can be reduced to maintain the ratio thus give the same boosted level. This gives an advantage in a reduction of chip area, time taken to boost the supply voltage, power and on-chip noise generated by the circuit.
Pump circuits are also known and are not discussed further herein. Briefly, a pump circuit relies on several capacitively coupled stages, isolated by diodes, to progressively raise the voltage to the required level. These stages are driven by non-overlapping clocks. A reduction of the capacitance to be raised is also advantageous for these circuits.
In an existing memory array, the power supply line to be boosted is connected to all the cells in a row of the memory and to the peripheral circuits for driving the wordlines. Thus, there is a significant amount of capacitance connected to the supply line when the supply voltage is boosted. The present invention seeks to reduce the capacitance connected to the power supply line when the supply voltage is boosted in order to overcome these problems.
Random access memories (RAM) having so-called divided wordline (DWL) architectures are known, in which a wordline is divided into independently addressable sub-wordlines. This improves memory speed by avoiding long wordlines and the associated larger resistances and capacitances. It would be desirable to use DWL architecture in so-called flash memories, that is memories made up of electrically erasable and programmable single floating gate transistor cells, to utilise its speed advantages. However, in these memories, problems arise in routing different voltage levels to the gates of the cells and keeping sub-wordline drive circuits relatively simple and hence small. It will be appreciated that there is a trade-off between improvement in speed using a DWL architecture and area consumed by the required sub-wordline drive circuits. Problems associated with routing different voltages to the gates of the cells are compounded when the voltage supply level has to be increased by pumping or boosting. Furthermore, sub-wordline drive circuits increase the capacitance on the voltage line to be boosted.